In modern semiconductor processing, transistor gate to contact spacing is a major limiting factor in achieving smaller pitch during scaling and/or shrinking of integrated circuits. Generally, a sufficiently large spacing between a contact and gate can overcome contact to gate alignment variations. When such spacing is relatively small, a lightly doped drain (LDD) may become connected to a contact due to alignment variations. As a result, there may be reliability concerns regarding hot electrons for NMOS devices or hot holes for PMOS devices.
FIG. 1 shows a cross-section view 100 of a conventional transistor structure. Shallow trench isolation (STI) portions 104 can surround a transistor active area in substrate 102. Source and drain doping profiles can include heavily doped drain (HDD) regions 108, and LDD regions 106. Source and drain contacts 110 can be spaced away from gate 112, where typically source side spacing “S1” is the same as drain side spacing “S2.” Such gate to source/drain spacings can be a limiting factor in transistor pitches, such as in memory devices (e.g., word line decoders).